Performance Evaluation of Networks On-chip Topologies

Abstract

The main objective of this project is to evaluate the performance of some well-known topologies that have been proposed for Networks-on-Chip including the mesh and torus. Whereas existing studies have focused on the graph-theoretical merits of such topologies, our study examines the performance of networks-on-chip taking into account the constraints imposed by implementation technology. The most relevant constraint for networks-on-chip is the wiring density of the chip. To achieve our goal, we have developed a simulation model using the discrete-event simulation technique. Extensive simulation experiments have been performed and the collected results indicate that while the bidirectional torus has superior performance when technological constraints are ignored due to its richer connectivity, its performance degrades considerably compared to the mesh once technological constraints are considered. Our results also indicate that the 2D topologies are more suitable for networks-on-chip than their 3D counterparts as they are a better fit for practical implementations.