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Élément Dublin Core | Valeur | Langue |
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dc.contributor.author | Ahmed shuaib, Abdurahman | - |
dc.date.accessioned | 2021-04-25T08:07:51Z | - |
dc.date.available | 2021-04-25T08:07:51Z | - |
dc.date.issued | 2019 | - |
dc.identifier.uri | http://di.univ-blida.dz:8080/jspui/handle/123456789/11327 | - |
dc.description | 621.926 ; 67 p | fr_FR |
dc.description.abstract | This thesis explores the design, implementation and performance of turbo codes by varying the frame length, the number of iterations and the decoding algorithm at the decoder. A turbo encoder consists of two Recursive Systematic Convolutional (RSC) encoders connected in parallel and separated by an interleaver. Its output consists of systematic bits (information bits) and the parity bits. During decoding, the decoder receives the codeword and computes the Log like Ratios (LLRs) using either log MAP or MAX log MAP algorithm. Iterative decoding is done on the decoded LLRs for better output. The comparison between the results of the two algorithms shows that log MAP algorithm gives better BER results but at the cost of the execution time while MAX log MAP gives slightly lower BER performance with reduced execution time | fr_FR |
dc.language.iso | fr | fr_FR |
dc.publisher | Univ Blida1 | fr_FR |
dc.subject | Turbo code, BER, Shannon, RSC, interleaver, parity bits, LLRs, iterative | fr_FR |
dc.title | STUDY OF TURBOCODESPERFOMANCES | fr_FR |
Collection(s) : | Mémoires de Master |
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Untitled.pdf | 1,31 MB | Adobe PDF | Voir/Ouvrir |
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