Please use this identifier to cite or link to this item:
http://localhost:8080/xmlui/handle/123456789/38713Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Larcher, Philippe | - |
| dc.date.accessioned | 2025-04-14T09:16:02Z | - |
| dc.date.available | 2025-04-14T09:16:02Z | - |
| dc.date.issued | 1997 | - |
| dc.identifier.isbn | 2212095848 | - |
| dc.identifier.uri | https://di.univ-blida.dz/jspui/handle/123456789/38713 | - |
| dc.language.iso | fr | fr_FR |
| dc.publisher | Eyrolles | fr_FR |
| dc.subject | VHDL (langage de description de matériel informatique) | fr_FR |
| dc.title | VHDL:introduction à la synthèse logique | fr_FR |
| dc.type | Book | fr_FR |
| Appears in Collections: | Livres | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 2-004-17.pdf | 904,44 kB | Adobe PDF | View/Open |
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