Design of a CMOS Frequency Divider for Phase-Locked Loop @2.4GHz

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Élément Dublin Core	Valeur	Langue
dc.contributor.author	HABOUSSI, Hamza Zineddine	-
dc.date.accessioned	2023-10-05T08:29:39Z	-
dc.date.available	2023-10-05T08:29:39Z	-
dc.date.issued	2023	-
dc.identifier.uri	https://di.univ-blida.dz/jspui/handle/123456789/25268	-
dc.description	4.621.1.1227 /p 91	fr_FR
dc.description.abstract	Abstract: operating at 2.4GHz. The design and analysis were performed using Cadence Virtuoso with the CMOS 90nm process. The behavioral models, implemented using the hardware description language Verilog-A, were utilized for all other blocks of the PLL system. The results demonstrate the successful integration and functionality of both types of dividers. The study contributes to the understanding of PLL operation and highlights the differences between Integer-N and Fractional-N dividers.	fr_FR
dc.language.iso	en	fr_FR
dc.publisher	blida 1	fr_FR
dc.subject	Phase-Locked Loop, CMOS Technology, Frequency Divider, Integer-N PLL, Fractional-N PLL, Behavioral modeling, Verilog-A, Cadence virtuoso.	fr_FR
dc.title	Design of a CMOS Frequency Divider for Phase-Locked Loop @2.4GHz	fr_FR
dc.type	Other	fr_FR
Collection(s) :	Mémoires de Master

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