Design of a CMOS Frequency Divider for Phase-Locked Loop @2.4GHz

Abstract

Abstract: operating at 2.4GHz. The design and analysis were performed using Cadence Virtuoso with the CMOS 90nm process. The behavioral models, implemented using the hardware description language Verilog-A, were utilized for all other blocks of the PLL system. The results demonstrate the successful integration and functionality of both types of dividers. The study contributes to the understanding of PLL operation and highlights the differences between Integer-N and Fractional-N dividers.