Résumé:
The main objective of this project is to conduct a performance evaluation of some well-known
topologies that have been proposed for Networks-on-Chip (NoC) including the Mesh and
Express Cube along with its variations. This later is based on a simple Mesh interconnection
network augmented by long-hop wires called express channels to enable bypassing of
intermediate hops for non-local communication. Whereas existing studies have focused on
the graph-theoretical merits of such topologies, our present study examines the performance
of networks-on-chip taking into account the constraints imposed by implementation
technology. The most relevant constraint for NoC systems is the wiring density of the chip. To
achieve our goal, we have developed a simulation model using the discrete-event simulation
technique. Extensive simulation experiments have been performed and the collected results
have then been analysed using statistical methods. Our results reveal that while the Express
Cube has superior performance when technological constraints are ignored due to its richer
connectivity, its performance degrades considerably compared to the Mesh when
technological constraints are taken into consideration. Our results also indicate that the 4
Hops variation of the Express Cube is the more suitable for Networks-On-Chip among the
Express Cube variations as it is a better fit for designs with large number of cores.
Keywords: Performance evaluation, Network-On-Chip, Mesh, Express Cube, Simulation,
Discrete-Event Simulation.
